Test MP+dmb.sy+addr-fri-rfi-addr-[fr-rf]

AArch64 MP+dmb.sy+addr-fri-rfi-addr-[fr-rf]
"DMB.SYdWW Rfe DpAddrdR Fri Rfi DpAddrdR FrLeave RfBack Fre"
Cycle=Rfi DpAddrdR FrLeave RfBack Fre DMB.SYdWW Rfe DpAddrdR Fri
Relax=
Safe=Rfi Rfe Fri Fre DMB.SYdWW DpAddrdR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpAddrdR Fri Rfi DpAddrdR FrLeave RfBack Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X9=x;
2:X1=x;
}
 P0          | P1                  | P2          ;
 MOV W0,#2   | LDR W0,[X1]         | MOV W0,#1   ;
 STR W0,[X1] | EOR W2,W0,W0        | STR W0,[X1] ;
 DMB SY      | LDR W3,[X4,W2,SXTW] |             ;
 MOV W2,#1   | MOV W5,#1           |             ;
 STR W2,[X3] | STR W5,[X4]         |             ;
             | LDR W6,[X4]         |             ;
             | EOR W7,W6,W6        |             ;
             | LDR W8,[X9,W7,SXTW] |             ;
             | LDR W10,[X9]        |             ;
Observed
    z=1; y=1; x=2; 1:X8=2; 1:X6=1; 1:X3=0; 1:X10=1; 1:X0=1;
and z=1; y=1; x=2; 1:X8=2; 1:X6=1; 1:X3=0; 1:X10=0; 1:X0=1;
and z=1; y=1; x=1; 1:X8=2; 1:X6=1; 1:X3=0; 1:X10=0; 1:X0=1;
and z=1; y=1; x=1; 1:X8=1; 1:X6=1; 1:X3=0; 1:X10=0; 1:X0=1;